Integrated circuit operating voltages are being rapidly decreased to permit the use of shorter gate length transistors and to obtain lower power consumption. However, a total system typically requires the use of several integrated circuit chips, some of which will be older designs using higher voltage. Thus, many customers request that the new low voltage chips include input/output circuits that interface with the higher voltage chips. Having transistors designed for two different voltages increases the cost of the process and added process steps also decrease yield.
CMOS transistors are manufactured with a process whereby a layer of gate oxide is disposed over a defined active region in the substrate, followed by the formation of a gate electrode over the gate oxide. Thereafter, source and drain regions are formed on either side of the gate electrode with a self-aligned process to form a channel region therebetween. As technology has advanced, the oxide thicknesses have been reduced to thickness on the order of 20 to 100 Angstroms for small signal devices. However, when the oxide thickness is reduced to such levels, the breakdown voltage for these transistors becomes rather small. For most small signal applications on a particular integrated circuit, this oxide thickness and breakdown voltage can be tolerated. However, when high voltage transistors are incorporated on the same substrate with the lower voltage transistors, this results in a mix of high voltage and low voltage transistors.
In U.S. Pat. No. 5,468,666, issued Nov. 26, 1995, to R. A. Chapman, which patent is incorporated herein by reference, a process is disclosed whereby high voltage and low voltage transistors are formed on the same substrate. In order to form both types of transistors, different doping levels were employed in the gate electrodes of the transistors to determine whether the transistor was a high voltage transistor or a low voltage transistor. Since the thickness of the depletion region that forms adjacent the gate oxide within the gate electrode is dependent upon the doping level, by varying this doping level, the effective oxide thickness can be varied. If the doping level is decreased, the effective oxide thickness will increase and, subsequently, the breakdown voltage of the transistor will increase.
In the Chapman patent, the variation of the doping level between transistors on the same substrate having a gate formed in the same layer is achieved by a masking process. Prior to defining and etching the gate electrodes in the polycrystalline silicon layer, the gates of the low voltage transistors were exposed and an implant made into the polycrystalline silicon layer. However, subsequent processing resulted in the formation of the source/drain implants, which required more dopants to be implanted into the substrate. At this point in the process, the upper surfaces of the gate electrodes were not protected and additional dopants associated with the source/drain implant operation were implanted into all of the transistors, both low voltage and high voltage transistors.
Two additional methods that have been utilized to manufacture different transistor types for two different supply voltages are (1) the split gate oxide method utilizing two different gate oxide thicknesses with one poly gate level and (2) a double poly process with different gate oxide thicknesses each under a different poly level. The split gate oxide process requires that a resist patterning be made on one of the gate oxides such that this initial gate oxide can be etched off some regions of the chip before a second gate oxide is grown. This patterning of resist lowers yield and reliability of the first gate oxide and requires special equipment for etch of gate oxide in the present resist. Logic circuits seldom utilize more than one poly level unless some type of SRAM memory is fabricated that has poly resistor loads or stacked active loads. If an extra poly deposition is added for input/output circuits, process yield will be lower to some extent. One of the most significant problems is the formation of second level poly filaments adjacent to the first level poly gates. These second level filaments are created along the edges of the first level poly at the time of the anisotropic etch of the second level poly. Extreme over etch of the second poly may be required and this etch could break through the first gate oxide where there is no first level poly. Another approach is to oxidize the filaments, but this process may oxidize too much of the first and second level poly gates. A double level poly process introduces much more difficulty than a simple .times.2 to a single level poly process.